 petrbalvin
|
4066396226
|
feat(asm): encode the GETCALLERPC, REM, DWORD and half-FCVT shapes
Assisted-by: GLM 5.3 Flash
|
2026-10-07 21:34:30 +02:00 |
|
|
petrbalvin
|
df7a5091e0
|
test(asm): pair the same-named GOROOT functions in definition order
Assisted-by: GLM 5.3 Flash
|
2026-10-07 21:34:30 +02:00 |
|
|
petrbalvin
|
c27ba30862
|
feat(asm): encode the arm64 local-exec TLS load
Assisted-by: GLM 5.3 Flash
|
2026-10-07 21:34:30 +02:00 |
|
|
petrbalvin
|
5f6be4584d
|
fix(asm): encode the flag-setting logicals to ZR and fold immediate expressions
Assisted-by: GLM 5.3 Flash
|
2026-10-07 21:34:30 +02:00 |
|
|
petrbalvin
|
c1cef7b6e8
|
feat(asm): materialise frame-relative addresses the way the toolchain does
Assisted-by: GLM 5.3 Flash
|
2026-10-07 21:34:30 +02:00 |
|
|
petrbalvin
|
1120a52a54
|
test(asm): sweep every registered amd64 extension mnemonic from .s text
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:56:25 +02:00 |
|
|
petrbalvin
|
fa50521619
|
feat(lint): surface the amd64 extension layer's refusals
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:56:25 +02:00 |
|
|
petrbalvin
|
76f8ba6403
|
feat(asm): give riscv64 the END and GETCALLERPC the toolchain accepts
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:39:44 +02:00 |
|
|
petrbalvin
|
0211d6672d
|
feat(asm): expand riscv64 memory offsets beyond the 12-bit immediate
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:39:44 +02:00 |
|
|
petrbalvin
|
7aba29ac67
|
test(arch): pin the golden vectors of the last four families
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:42 +02:00 |
|
|
petrbalvin
|
aeb109a64c
|
feat(arch): the vector-length arithmetic pseudo group
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
bd85f8838d
|
feat(arch): the SVE2.1 last-active vector and compare families
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
12a5cfff52
|
feat(arch): the rest of the SVE2 BFloat16 wall
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
cdc3a75c88
|
feat(arch): the SVE multiple-structure loads and stores
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
82dbf087a8
|
feat(arch): the SVE2 BFloat16 arithmetic core
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
0760cc91af
|
feat(arch): the SVE2 three-source and bitwise combine families
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
bd80499c74
|
feat(arch): the SVE2 shift-by-vector family
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
b93fccc075
|
feat(arch): the SVE2.1 pairwise and quadword-reduction families
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
31ab584eee
|
feat(arch): the SVE2.1 narrowing two-to-one family
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
ee2c6d51b3
|
fix(arch): keep Zdn out of the class bits of the predicated Z-alias source
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:35:41 +02:00 |
|
|
petrbalvin
|
6e49cbd099
|
feat(asm): assemble the extended instruction layer on amd64
Assisted-by: GLM 5.3 Flash
|
2026-10-07 20:24:51 +02:00 |
|
|
petrbalvin
|
d4878524e8
|
test(asm): pin the clean GOROOT arm64 set against the toolchain
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:54:22 +02:00 |
|
|
petrbalvin
|
07f4622ffe
|
style(asm): range over the kernel generator's statement count
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:54:22 +02:00 |
|
|
petrbalvin
|
b3ede5f952
|
test(asm): pin the mid-function pool flush against the toolchain
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:54:22 +02:00 |
|
|
petrbalvin
|
5a5936d222
|
feat(asm): drain the arm64 literal pool mid-function at the distance bound
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:54:22 +02:00 |
|
|
petrbalvin
|
4632ac1bb9
|
feat(arch): add the AVX-VNNI-INT16 dot products to the extension layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:49:15 +02:00 |
|
|
petrbalvin
|
27ef71859b
|
feat(arch): add VMINMAXSH to the extension layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:49:15 +02:00 |
|
|
petrbalvin
|
03f9ef0ac6
|
feat(arch): add the FP16 complex fused multiply-add to the extension layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:49:15 +02:00 |
|
|
petrbalvin
|
86cb785e58
|
fix(asm): read the MOV family registers against their banks
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:40:32 +02:00 |
|
|
petrbalvin
|
d18195f581
|
test(asm): pin the riscv64 error parity against the toolchain catalogues
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:40:32 +02:00 |
|
|
petrbalvin
|
f0942ff7f3
|
fix(asm): reject the operand shapes the toolchain rejects on riscv64
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:40:32 +02:00 |
|
|
petrbalvin
|
6c66f5bbd9
|
test(asm): encode the new FP16 families through the registry
Assisted-by: GLM 5.3 Flash
|
2026-10-07 19:00:44 +02:00 |
|
|
petrbalvin
|
509afbb6c9
|
feat(arch): add the FP16 complex multiply and minimum-maximum to the extension layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 18:59:09 +02:00 |
|
|
petrbalvin
|
8080e0acef
|
feat(arch): add the AVX512-FP16 FMA families to the extension layer
Assisted-by: GLM 5.3 Flash
|
2026-10-07 18:58:49 +02:00 |
|
|
petrbalvin
|
acd30088af
|
fix(asm): reject the operand-starved riscv64 spellings instead of panicking
Assisted-by: GLM 5.3
|
2026-10-07 13:53:37 +02:00 |
|
|
petrbalvin
|
d03de62c07
|
feat(arch): add the amd64 fp16 packed imm8-control group
Assisted-by: GLM 5.3
|
2026-10-07 13:51:48 +02:00 |
|
|
petrbalvin
|
8de1b371da
|
feat(arch): add the amd64 fp16 packed conversion family
Assisted-by: GLM 5.3
|
2026-10-07 13:51:48 +02:00 |
|
|
petrbalvin
|
fb6d01a7d0
|
feat(arch): encode the amd64 embedded rounding and SAE decorations
Assisted-by: GLM 5.3
|
2026-10-07 13:51:48 +02:00 |
|
|
petrbalvin
|
104bea036b
|
feat(asm): encode the arm64 SVE gather loads and scatter stores
Assisted-by: GLM 5.3
|
2026-10-07 13:51:10 +02:00 |
|
|
petrbalvin
|
6faf850793
|
feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
|
2026-10-07 13:51:10 +02:00 |
|
|
petrbalvin
|
dac0a5b51b
|
docs(asm): state the seed layout of the arch fuzz targets exactly
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
965b33e5b0
|
test(asm): seed the riscv64 and loong64 assemble fuzz targets
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
b9dfb48d79
|
fix(asm): encode the loong64 64-bit-span 2RI14 offsets like the toolchain
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
41aa8edfd2
|
fix(asm): match the toolchain's loong64 logical immediate expansion
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
8fdc511d0d
|
test(asm): add the loong64 error-parity catalogue
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
e5035d92e9
|
fix(asm): reject the offset on the loong64 register-indexed memory form
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
b54547c08d
|
fix(asm): reject the shifted-register compositions on loong64
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
e9510e8a68
|
test(asm): pin the riscv64 tail against the toolchain byte for byte
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
9d50212a71
|
fix(asm): refuse the riscv64 width moves across register banks
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|
|
petrbalvin
|
f2892e4f59
|
feat(asm): emit the riscv64 local-exec TLS sequence
Assisted-by: GLM 5.3
|
2026-10-07 13:51:02 +02:00 |
|