Commit Graph
100 Commits
Author SHA1 Message Date
petrbalvin 8080e0acef feat(arch): add the AVX512-FP16 FMA families to the extension layer
Assisted-by: GLM 5.3 Flash
2026-10-07 18:58:49 +02:00
petrbalvin 87493d9391 build(justfile): anchor the fuzz recipe to one exact target
Test / test (push) Successful in 1m2s
Assisted-by: GLM 5.3
2026-10-07 15:00:28 +02:00
petrbalvin 63ed141522 fix(parser): reject macro parameter lists the toolchain rejects
The C variadic spellings ("..." and the GNU "name..."), an empty or
trailing parameter, a missing comma, a stray token and an unterminated
list all parsed silently before: non-identifier tokens were skipped, so
"#define M(...)" defined a zero-parameter macro and invocations were
diagnosed only by argument count, if at all.  The toolchain rejects the
definition itself ("bad definition for macro"), and so does the
preprocessor now: the parameter list must be identifiers separated by
single commas and closed by the parenthesis, and a rejected definition
leaves the name unbound.  The spellings join the fuzz corpus.

Assisted-by: GLM 5.3
2026-10-07 14:04:15 +02:00
petrbalvin 373ec51061 fix(format): treat a selector-folded label as naming its macro
The lexer folds NAME.selector into one identifier, and an object macro
reached through the selector expands with it travelling along, so a
label spelled NAME.selector: restructures exactly like the bare name
would.  The macro-name checks now resolve the prefix before the first
period, and the crashing input joins the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin f932c5811c fix(format): never peel a stacked label that names a macro
Peeling a stacked label whose name is a macro moves it onto a line of
its own, where its expansion decides the line's shape: an empty body
leaves a bare colon behind, a line the parser rejects.  The peel loops
now hold such labels back with the rest of the line, and the crashing
input joins the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin b54d2b4520 fix(format): keep macro content behind a label on its line
The canonical form splits a label from the instruction that follows it,
but an identifier naming a macro may expand into any token at all: moved
to a line of its own it no longer parses, because the parser accepts a
non-mnemonic first token only behind a label.  The names #define'd in
the file now hold such content back, conservatively across the whole
file, and the crashing input joins the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin f452b8a995 fix(format): keep a macro-named label line whole
A label whose name is a macro expands into whatever the body is, so the
line's statement structure exists only after expansion; splitting the
label off changed clean input into a different statement sequence.  The
formatter now records the names #define'd above each line and renders
such a label line unsplit, and the crashing input joins the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 715298ed23 test(format): keep the expansion signature off the EOF comment newline
An unterminated block comment at the end of a file swallows the
formatter's mandatory final newline, an artifact the token view already
documents as layout; the preproc signature entry now trims it so the
invariant stays about tokens.  The triggering input joins the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin bbe14dd1ab fix(parser): diagnose GLOBL and DATA without a symbol name
A bare GLOBL or DATA parsed without a single diagnostic while leaving a
nil Name in the tree, a pointer every downstream tool dereferences; TEXT
keeps a placeholder beside its error for exactly that reason, and GLOBL
and DATA now do the same.  The crashing input enters the corpus.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 05de774c0a test(format): pin the macro-layout crashers as corpus seeds
The two inputs the expansion round-trip target was built for, the object
macro with a parenthesised body and the continuation-only macro body,
enter the seed corpus so every plain go test run replays them.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 6218023a63 style(parser): range over the include chain depth
Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 71cc65ea48 fix(format): separate an empty TEXT body from the next block
The one-blank rule before a new block skipped every line that followed a
TEXT directive, not just the function's first label, so a TEXT with an
empty body ran straight into the next declaration.  The exemption now
applies to labels only, and the directive shapes around GLOBL and DATA
ranges are pinned.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 21b6348dbe test(parser): cover self-includes, deep chains and diamonds
The include guard's scope is now pinned from three sides: a file
including itself is a cycle diagnostic, a chain of two thousand distinct
headers completes with the deepest content spliced, and a header reached
again through a separate branch splices a second time and is refused as
a redefinition.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 32c453d66e test(format): corpus invariants over GOROOT assembly
Three property tests walk every .s file under the installed GOROOT plus
the repository's kernels: formatting is idempotent and preserves the
token stream, a clean parse keeps its tree through a format pass, and a
cleanly expanding file expands to the same statements afterwards.  The
walks skip under -short so the push suite keeps its budget.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin 59637d35b1 test(format): fuzz the expansion round-trip
A second formatter target holds the assembly path's contract: beyond the
token view, a file the expander reads cleanly must expand to the same
statement sequence after formatting, because the macro language draws
distinctions from layout (the adjacency of a #define name and its '(',
continuation bodies) that a token count cannot see.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin e600fc00e7 fix(format): preserve macro adjacency and continuation bodies
The canonical spelling of a #define line glued a '(' to the macro name
whatever the input's spacing, turning an object macro whose body opens
with a parenthesis into a parameterised one, and it flattened the
backslash continuations of a multi-line body into one physical line,
fusing the statements the expansion splits at those boundaries.  Both
change what a valid file assembles to, so renderPreproc now keeps the
name's adjacency (the same column check the preprocessor applies) and
restores the continuation boundaries from the token positions.

Assisted-by: GLM 5.3
2026-10-07 13:54:42 +02:00
petrbalvin acd30088af fix(asm): reject the operand-starved riscv64 spellings instead of panicking
Assisted-by: GLM 5.3
2026-10-07 13:53:37 +02:00
petrbalvin d03de62c07 feat(arch): add the amd64 fp16 packed imm8-control group
Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin 8de1b371da feat(arch): add the amd64 fp16 packed conversion family
Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin fb6d01a7d0 feat(arch): encode the amd64 embedded rounding and SAE decorations
Assisted-by: GLM 5.3
2026-10-07 13:51:48 +02:00
petrbalvin e56c04e9ee fix(asm): read three operands from the arm64 last-element form
Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
petrbalvin 104bea036b feat(asm): encode the arm64 SVE gather loads and scatter stores
Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
petrbalvin 6faf850793 feat(asm): encode the arm64 SVE2 crypto, counter and reduction families
Assisted-by: GLM 5.3
2026-10-07 13:51:10 +02:00
petrbalvin dac0a5b51b docs(asm): state the seed layout of the arch fuzz targets exactly
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 965b33e5b0 test(asm): seed the riscv64 and loong64 assemble fuzz targets
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin b9dfb48d79 fix(asm): encode the loong64 64-bit-span 2RI14 offsets like the toolchain
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 41aa8edfd2 fix(asm): match the toolchain's loong64 logical immediate expansion
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 7f955f8bd1 fix(cmd/gasm): probe the loong64 sc.q operand order in the encodability battery
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 8fdc511d0d test(asm): add the loong64 error-parity catalogue
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin e5035d92e9 fix(asm): reject the offset on the loong64 register-indexed memory form
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin b54547c08d fix(asm): reject the shifted-register compositions on loong64
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin e9510e8a68 test(asm): pin the riscv64 tail against the toolchain byte for byte
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 9d50212a71 fix(asm): refuse the riscv64 width moves across register banks
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin f2892e4f59 feat(asm): emit the riscv64 local-exec TLS sequence
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin f8dbd4f017 fix(asm): lower the riscv64 immediate CSR pseudos onto their opcode forms
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin e5aabf9801 fix(asm): encode the riscv64 FENCE predecessor and successor flags
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin 36d1ac804a fix(asm): route the riscv64 register moves through the toolchain forms
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin da35883633 fix(asm): compress the riscv64 two-operand arithmetic and immediate tail
Assisted-by: GLM 5.3
2026-10-07 13:51:02 +02:00
petrbalvin f0318d2c99 test(disasm): pin the vector spaces the decoder refuses
The RISC-V vector extension and the LoongArch LSX/LASX families carry
no x/arch decode tables, and the loong64 WORD directive is no
instruction: all three stay on the placeholder.  The pins record
today's refusal with the corpus rows that assemble the same bytes, so
a decoder bump that learns one of these spaces flips a row here and
asks for the naming pass to cover it.

Assisted-by: GLM 5.3
2026-10-07 13:50:54 +02:00
petrbalvin a7f9d5eb67 feat(disasm): render the loong64 families x/arch names Unknown
x/arch's Plan 9 renderer decodes thirty-odd scalar loong64 operations
perfectly but prints them as "Unknown OP args", and names the
sign-extension pair EXT.W.B/EXT.W.H "?".  The supplementary naming
pass re-renders them with the toolchain's own spellings: the families
whose operand order x/arch already prints the Plan 9 way trade only
the mnemonic, and the pointer loads and stores, the acquire loads,
the release stores, PRELD and ALSL are rebuilt from the decoded
arguments with the toolchain's operand order and its raw displacement
reading.  ADDU16I.D, a macro helper the assembler never takes as
input, keeps the decoder's Unknown render.

The loong64 parity fixture grows from 73 to 385 rows, pinning every
unique four-byte corpus word the decoder accepts, and the LL/SC
displacement divergence in the encoder is documented for asm.

Assisted-by: GLM 5.3
2026-10-07 13:50:54 +02:00
petrbalvin 0f6e008c9a feat(disasm): name the arm64 words arm64asm refuses
arm64asm rejects three exception-space words the toolchain's corpus
assembles: the hypervisor call HVC, the secure monitor call SMC and
the speculation barrier SB.  The supplementary naming table reads
the raw word in the error branch and renders the corpus spellings;
the corpus rows are pinned in the parity fixture and the boundary
test holds the unallocated neighbours on the placeholder.

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin 3f35b2a718 fix(disasm): drop the implicit GOARCH constraint the naming files carried
The names naming_amd64.go and naming_amd64_test.go carried the _amd64
filename suffix, which the go tool reads as an implicit GOARCH=amd64
build constraint: the tables disappeared from every non-amd64 build
and the package failed to compile for arm64, riscv64 and loong64, the
other three architectures the tool assembles.  Renaming to
amd64_naming.go removes the constraint; the module builds again for
all four GOARCH values.

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin 2c70359ad0 feat(disasm): name the amd64 encodings x86asm refuses
The toolchain's assembler corpus carries 195 amd64 encodings the
x/arch decoder rejects or degenerates: the BMI1/BMI2 VEX families
(ANDN, BEXTR, BLSI, BLSMSK, BLSR, BZHI, MULX, PDEP, PEXT, RORX,
SARX, SHLX, SHRX), the 0F 01 quartet CLAC, STAC, RDPKRU and WRPKRU,
the bare and REX-only RDSEED forms, and UD1.  The supplementary
naming table decodes the VEX prefix and the ModR/M shape and renders
the toolchain's own spellings; every corpus row is pinned in the
unlisted fixture and round-trips byte for byte through the encoder,
and the boundary test pins the prefix shapes no family carries.

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin d98aadbbbf test(disasm): drop the closed byte-width divergences from the parity map
The operand-width reconciliation closes the byte-register fixture lines
byte for byte: XADDL, XCHGL, CMPXCHGL and CRC32 with byte registers, the
ALU and TEST immediates against AL and DL, and the unlisted accumulator
short forms.  MOVL $0x7, DL stays mapped for the legal-encoding choice
alone: the toolchain's own table says "c6c207 or b207", go tool asm emits
b207, and the fixed-point invariant holds with it.

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin 8bded3ea39 test(asm): pin the byte-form width reconciliation and its oracle
Table-driven rows for the renderer's spellings (the L suffix or none with
a byte register encodes the byte form, every register joining at its low
byte), the refusals (W, Q and the MOVD alias take no byte register) and a
differential kernel of the B-suffixed spellings assembled through both
gasm and go tool asm, byte for byte.

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin 98a562d8b3 fix(asm): settle the byte-form width from the register operands
The suffixed scalar families derived the operand width from the mnemonic
alone, so a byte-spelled register under the L spelling or no suffix at all
encoded the widened form: XADDL DL, DL emitted 0F C1 where the byte form is
0F C0, CMPL AL, $7 emitted the 32-bit immediate form where the AL form is
3C 07, and CRC32 DL, R11 widened past the F0 byte opcode.  operandWidth now
reconciles the suffix with the operands: a byte register (AL, DL, R8B, ...)
forces the 8-bit form, which is the text the toolchain's own disassembly
prints for those encodings, while the W and Q spellings never ride a byte
register and are refused as go tool asm refuses them (MOVQ AL, AX).  The
shift count and the two- and three-operand IMUL forms stay out of the
reconciliation, and the byte accumulator short forms now belong to the AL
spelling alone, matching the toolchain's division (ADDB $3, AX is
80 c0 03, TESTB $7, AX is f6 c0 07).

Assisted-by: GLM 5.3
2026-10-07 13:49:58 +02:00
petrbalvin 33e7fdac98 fix(asm): enforce the arm64 TLBI, RPRFM, FCVT and integer-pair arities
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 7a69be8b59 fix(asm): reject the arm64 REGTMP spellings the toolchain refuses
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 2385bb7069 fix(asm): enforce the arm64 VLD/VST post-index contract
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 7bc80ccb54 fix(asm): emit nothing for the arm64 NOP pseudo-instruction
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 405e2427ed fix(asm): place the arm64 literal pool the way the toolchain flushes it
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 4fc96decc4 fix(asm): size the arm64 logical-immediate materialisation exactly
Assisted-by: GLM 5.3
2026-10-07 13:49:49 +02:00
petrbalvin 4ccd3bb4c6 test(debug): put the dead-debuggee and kill audits on deterministic ground
The launch-failure audit raced the clock: it asserted the dead debuggee
surfaced within 1.5 seconds, a bound the loaded machine behind a ten-way
test storm regularly starved past even though the poll detects the dead
notice within milliseconds of its appearance.  The audit now proves the
property itself: a stub debuggee that starts in single-digit milliseconds
marks itself dead, so the notice is always inside the poll's budget and
the error must come from the dead-file watch, while the real binary is
checked without any wall-clock bound.  A companion audit drives Kill
through a parked, a doubly killed and a run-to-exit session, the states
whose cleanup used to hang the package, under a watchdog.

Assisted-by: GLM 5.3
2026-10-07 13:46:29 +02:00
petrbalvin b5d6f1b46a fix(debug): target the traced thread and keep the kill from ever blocking
The Go runtime can migrate the debuggee's target-mode goroutine off the
process leader before PTRACE_TRACEME, which left the trace relation on a
thread the session never addressed: its stops starved the waits on the
leader, and a kill sequence that resumed nothing and then blocked in
Wait4 hung the whole package.  The debuggee now reports the traced thread
in the launch handshake and parks with a thread-directed stop, every
ptrace request and wait addresses that thread, a SIGURG arriving on a
single-step resumes it as a single-step again instead of letting the
tracee run uncontrolled, a resume rejected with ESRCH lifts a group-stop
with SIGCONT and retries once, and Kill resumes, kills and reaps through
non-blocking waits so it returns for a tracee in any state.

Assisted-by: GLM 5.3
2026-10-07 13:46:18 +02:00
petrbalvin 409c8b348d fix(asm): bound the arm64 VTBL table list before the destination read
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 2b2a72d54e fix(asm): encode the arm64 bitfield aliases with their own opc
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 8ab99c9b0c fix(asm): tighten the arm64 acceptance toward the toolchain
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 82d741514a fix(asm): key the arm64 immediate class order on the ZR spelling
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin f20aa156d0 fix(asm): treat the arm64 $-8 frame as frameless and encode the RET forms
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin d853432dba fix(asm): route the arm64 logical immediates to ZR through REGTMP
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin fbdad8424f feat(asm): encode the arm64 FP immediate moves
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin a9b54b6868 fix(asm): carry the arm64 immediate to ZR through MOVZ
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin d786b90fa1 feat(asm): lower the arm64 con(register) form to the ADD chain
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 9ef14bdb71 feat(asm): encode the arm64 SIMD arrangement bits
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 458cdd2066 feat(asm): encode the arm64 register-offset addressing forms
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin a344399b81 fix(asm): set the CASALH opcode bit fifteen
The CASALH entry carried the CASB/CASH opcode pattern where the acquire
forms take the full fixed field, so the word differed from the
toolchain's in one opcode bit.  Pinned against the oracle word.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin a0fa7e802c feat(asm): pool the arm64 offsets the split bands cannot carry
Offsets beyond the split bands ride a per-function literal pool the way
the toolchain lays one out: a PC-relative literal load into REGTMP, then
the register-offset access (the pair family adds the base addition), the
pooled words appended after the last instruction behind the UNDEF guard,
deduplicated by value with the sign- and width-aware load selection.

The same differential pass against the corpus exposed three wrong-code
bugs and fixes them: the logical-immediate period marker rode the wrong
position for every element below 64 bits, so the 32-bit forms encoded a
different constant than written; the plain register operand of an
ADD/SUB against SP took the shifted-register form where the toolchain
uses the extended one with the identity extend, silently truncating
through UXTB; and the AUTIA1716 and AUTIB1716 hint constants were the
PACIA and PACIB encodings.  An offset sweep across every band boundary
now pins all three against the live oracle.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 71e8dd550d feat(asm): split wide arm64 load and store offsets into REGTMP
Offsets the single-instruction forms cannot carry lower the way the
toolchain lowers them: ADD or SUB moves the whole distance into REGTMP
within the ±4095 band, and the 24-bit band above it splits into an ADD of
the high half and an access of the low half, with the pair family taking
the two-ADD sequence.  The split band follows loadStoreClass per width,
byte accesses taking the full 24 bits and the Q width the widest, so an
offset the toolchain pools is never split instead.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 2bd52eb7ad fix(asm): scale the FLDPQ and FSTPQ pair offsets by sixteen
The pair encoder derived the imm7 divisor from the width suffix alone, so
the 128-bit FP pairs divided their offsets by eight and encoded twice the
distance.  The Q spellings scale by sixteen like every other 128-bit
access; the differential kernel carries them now.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin daf7fad5b9 feat(asm): encode the arm64 Q-width FP load and store
FMOVQ routes through the MOV load/store machinery in the plain, post-index,
pre-index and static-symbol forms.  The Q width carries its size in the opc
field, so the store spelling is opc=10 and the access scales by sixteen;
both come from helpers now instead of the size exponent.  The static-symbol
form takes the toolchain's twelve-byte ADRP + ADD + access fallback with the
R_ADDRARM64 pair.  The register-to-register and immediate forms stay
rejected, matching the toolchain's own table.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin a6bd9c1ebe feat(asm): encode the LDEORAL acquire variants
Assisted-by: GLM 5.3 Flash
2026-10-07 02:36:24 +02:00
petrbalvin 458d981f31 feat(disasm): name the CLDEMOTE encoding the decoder refuses
The hint NOP opcode 0F 1C /r with a memory operand is CLDEMOTE, a
memory-only instruction the toolchain's own table carries; the decoder
rejects the encoding instead of naming it.  The rejected-encoding side
of the supplementary table names it from the bytes, and the corpus row
0f1c03 pins the text in the unlisted fixture, round trip byte exact.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:27:51 +02:00
petrbalvin dd356b9e6a fix(disasm): name the amd64 families x/arch decodes to the zero opcode
x/arch reports the ADCX, ADOX, RDSEED, RDPID, TPAUSE, UMONITOR, UMWAIT
and ENDBR families with no error but the degenerate zero instruction,
which GoSyntax renders as Op(0) under its prefix decoration and with a
length of one.  A supplementary naming table keyed by the opcode
pattern restores the toolchain's own spellings and lengths; the parity
fixtures pin all 41 corpus rows (ENDBR32 alone, which the toolchain
cannot spell, pins as bytes and text in the focused naming test).

Assisted-by: GLM 5.3 Flash
2026-10-07 02:27:51 +02:00
petrbalvin 6c4932c4ec feat(arch): the SVE2.1 Z-alias permutations and copies
Assisted-by: GLM 5.3 Flash
2026-10-07 02:27:35 +02:00
petrbalvin 8231302bca feat(arch): the SVE predicate family in the extended layer
Assisted-by: GLM 5.3 Flash
2026-10-07 02:26:19 +02:00
petrbalvin 83052ab466 feat(lint): accept the wired extension mnemonics
Assisted-by: GLM 5.3 Flash
2026-10-07 02:23:37 +02:00
petrbalvin 9c951c232e feat(asm): assemble the extended instruction layer on arm64
Assisted-by: GLM 5.3 Flash
2026-10-07 02:23:37 +02:00
petrbalvin c2adde948f feat(arch): add the write mask to the packed amd64 destinations
Assisted-by: GLM 5.3 Flash
2026-10-07 02:21:57 +02:00
petrbalvin 631fb8a8d7 chore: keep the fuzz cache and pending reproductions out of the tree
Assisted-by: GLM 5.3 Flash
2026-10-07 02:14:37 +02:00
petrbalvin 470639cd68 test(asm): carry the fuzz pipeline to arm64
Assisted-by: GLM 5.3 Flash
2026-10-07 02:14:37 +02:00
petrbalvin e7a1c20467 fix(asm): prefix MOVQ2DQ with F3
The two bank-crossing quadword moves take the mandatory prefix by
direction: the toolchain renders F3 0F D6 as MOVQ2DQ with the MMX
source and F2 0F D6 as MOVDQ2Q with the XMM source, and the encoder
emitted F2 for both, so MOVQ2DQ encoded MOVDQ2Q.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:12:21 +02:00
petrbalvin 0cfed5516c fix(asm): carry the riscv64 U-type immediate raw
The toolchain writes the source immediate straight into imm[31:12]
(riscv64.s: AUIPC 24287, X10 encodes 7ffff517), and rejects values
beyond the signed 20-bit span; the encoder divided by 4096 instead and
truncated silently, so the high bits of every large AUIPC and LUI were
lost.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:12:21 +02:00
petrbalvin a829b8f321 fix(parser): read the segment-absolute rendering FS:0
The toolchain's disassembler prints the segment-prefixed disp32
absolute as FS:0, but the bare-name branch read the segment register
alone and dropped the offset, so MOVQ FS:0, DX silently encoded a
register move.  The colon-offset form now lowers to the same
segment-absolute operand the 0(FS) spelling takes.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:12:21 +02:00
petrbalvin abc2d32b83 fix(asm): encode the CMOV condition the renderer prints
The renderer spells a conditional move CMOV plus the condition alone
(CMOVLE, CMOVG), the width carried by the operand registers, so
CMOVLE parsed as the size L and the condition E and encoded CMOVE.
A suffix that is itself a condition name now reads as that condition
with the width from the destination register, and the Plan 9
size-prefixed spellings keep their parse.

Assisted-by: GLM 5.3 Flash
2026-10-07 02:12:21 +02:00
petrbalvin 11cac26508 feat(arch): add the scaled index to the amd64 memory operands
Assisted-by: GLM 5.3 Flash
2026-10-07 02:06:11 +02:00
petrbalvin ccb155437e feat(arch): add the {1toN} broadcast to the packed amd64 memory sources
Assisted-by: GLM 5.3 Flash
2026-10-07 02:06:11 +02:00
petrbalvin 9c1392dfc3 test(disasm): pin the amd64 lines the objdump listing fragments
Assisted-by: GLM 5.3 Flash
2026-10-07 01:57:04 +02:00
petrbalvin 8d611bfdaf feat(arch): add the remaining scalar FP16 memory forms to the extension layer
Assisted-by: GLM 5.3 Flash
2026-10-07 01:35:48 +02:00
petrbalvin 454a21f5b7 feat(arch): add the packed FP16 and BF16 memory forms to the extension layer
Assisted-by: GLM 5.3 Flash
2026-10-07 01:35:48 +02:00
petrbalvin d275dee3ae feat(arch): add the scalar FP16 memory forms to the amd64 extension layer
Assisted-by: GLM 5.3 Flash
2026-10-07 01:35:48 +02:00
petrbalvin 7d69dda874 feat(arch): add the amd64 memory-operand mechanism to the extension layer
Assisted-by: GLM 5.3 Flash
2026-10-07 01:35:48 +02:00
petrbalvin d1030a1788 test(verify): prove the arm64 lse atomics through the link-parity kernel
Assisted-by: GLM 5.3 Flash
2026-10-07 01:31:28 +02:00
petrbalvin 8e3b7f1caa test(verify): prove the amd64 sse families through the link-parity kernel
Assisted-by: GLM 5.3 Flash
2026-10-07 01:31:28 +02:00
petrbalvin b22abf512f test(verify): prove the riscv64 vector families through the link-parity kernel
Assisted-by: GLM 5.3 Flash
2026-10-07 01:31:28 +02:00
petrbalvin ffc23929c6 refactor(verify): extract the shared goobj link-parity harness
Assisted-by: GLM 5.3 Flash
2026-10-07 01:31:28 +02:00
petrbalvin a4a77b3168 build(justfile): lower the fuzz worker default to the fence the assembler target holds
Assisted-by: GLM 5.3 Flash
2026-10-07 01:15:42 +02:00
petrbalvin 380314a05f test(asm): keep the data-section ceiling out of the seed corpus
Assisted-by: GLM 5.3 Flash
2026-10-07 01:14:58 +02:00
petrbalvin de2f28504a test(asm): parse once and assemble twice in the fuzz body
Assisted-by: GLM 5.3 Flash
2026-10-07 01:14:58 +02:00
petrbalvin 7878112b93 fix(asm): bound the data section to what the image can materialise
Assisted-by: GLM 5.3 Flash
2026-10-07 01:14:58 +02:00
petrbalvin dd074dbafd fix(asm): reject an out-of-range GLOBL size with a diagnostic
Assisted-by: GLM 5.3 Flash
2026-10-07 01:13:40 +02:00